This book will explain how to verify SoC (Systems on Chip) logic designs using "formal" and "semiformal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity ...
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This book will explain how to verify SoC (Systems on Chip) logic designs using "formal" and "semiformal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
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Add this copy of Verification Techniques for System-Level Design: 1ed to cart. $77.68, new condition, Sold by Educational Media Centre rated 4.0 out of 5 stars, ships from New Delhi, DELHI, INDIA, published 2007 by Morgan Kaufmann Publishers.
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Add this copy of Verification Techniques for System-Level Design: 1ed to cart. $91.94, new condition, Sold by Basi6 International rated 5.0 out of 5 stars, ships from Irving, TX, UNITED STATES, published 2007 by Morgan Kaufmann Publishers.
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