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51. System-On-Chip for Real-Time Applications
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52. System-On-Chip for Real-Time Applications
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53. Language-Driven Exploration and Implementation of
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54. High Level Synthesis of Asics Under Timing and Syn
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56. High Level Synthesis of Asics Under Timing and Syn
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58. Language-Driven Exploration and Implementation of Partially Re-Configurable Asips
by Chattopadhyay, Anupam, and Leupers, Rainer, and Meyr, Heinrich
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59. Language-Driven Exploration and Implementation of Partially Re-Configurable Asips
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60. High Level Synthesis of ASICs under Timing and Synchronization Constraints
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61. Language-Driven Exploration and Implementation of Partially Re-Configurable Asips
by Chattopadhyay, Anupam, and Leupers, Rainer, and Meyr, Heinrich
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62. Language-Driven Exploration and Implementation of Partially Re-Configurable Asips
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63. Hardware Implementation of Finite-Field Arithmetic
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64. Hardware Implementation of Finite-Field Arithmetic
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65. Hardware Implementation of Finite-Field Arithmetic
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66. Hardware Implementation of Finite-Field Arithmetic (Electronic Engineering)
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67. Hardware Implementation of Finite-Field Arithmetic
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68. Hardware Implementation of Finite-Field Arithmetic (Electronic Engineering)
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69. Language-Driven Exploration and Implementation of Partially Re-Configurable Asips
by Anupam Chattopadhyay; Rainer Leupers; Heinrich Meyr; Gerd Ascheid
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70. Embedded Dsp Processor Design, : Application Specific Instruction Set Processors (Systems on Silicon) (Volume 2)
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